1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device that includes a circuit block composed of a plurality of standard cells.
2. Description of Related Art
A semiconductor device is typically designed by combining a plurality of needed standard cells to lay out circuit blocks having desired functions on a semiconductor substrate (see Japanese Patent Application Laid-open Nos. 2010-73728, 2000-77609, 2010-129895, and 2008-193070). “Standard cells” refer to pre-registered layouts of logic circuits having basic functions, such as an inverter circuit and a NAND gate circuit. Wirings for establishing internal connections of the standard cells are mainly formed on a first wiring layer that lies above a gate wiring layer. Wiring for connecting the standard cells, wiring for supplying input signals and power supply potentials from outside the circuit blocks, and wiring for supplying output signals to outside the circuit blocks are mainly formed on a second wiring layer that lies above the first wiring layer.
The wirings formed on the second wiring layer are typically laid out in one direction in parallel. The width of the wirings formed on the second wiring layer needs to be designed in consideration of characteristics (such as resistance) required for the wiring. In many cases, power supply wiring needs to be designed to have a greater wiring width than that of signal wiring. As the fine processing technology advances, standard cells having the same functions and the same characteristics may be made smaller than heretofore. Even in such cases, power supply wiring can be difficult to miniaturize in proportion to standard cells in order to satisfy characteristic requirements. A reduction in the size of standard cells has thus tended to increase the wiring density mainly of the second wiring layer.
The increased wiring density of the second wiring layer due to the miniaturization of standard cells matters little as long as the entire wiring can be properly laid out. However, the wiring may not always be able to be fully laid out. In such cases, wiring areas need to be secured by taking such measures as arranging free spaces and compensation capacitors between some standard cells. This increases the chip size.
Such a problem becomes pronounced as the types of power supply potentials needed for the circuit blocks increase. The reason is that, as mentioned above, the wiring width of power supply wiring is difficult to reduce. At least two types of power supply potentials are needed, including a high-level power supply potential (VDD) and a low-level power supply potential (VSS). Other examples include the well potential (VPW) of p-wells where n-channel metal oxide semiconductor (MOS) transistors are formed and the well potential (VNW) of n-wells where p-channel MOS transistors are formed. Under the circumstances, a technology for reducing the wiring density of a wiring layer lying above the gate wiring layer of a semiconductor device using standard cells has been desired.